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HP OpenVMS System Manager's Manual, Volume 2:... |
Managing Special Processing Environments |
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Understanding Vector Processing
Traditional (scalar) computers operate only on scalar values, and must process vector elements sequentially. Vector computers, on the other hand, recognize vectors as native data structures and can operate on an entire vector with a single vector instruction. Because this type of processing involves the concurrent execution of multiple arithmetic or logical operations, a vector computer can routinely process a vector four to five times faster than a traditional computer can using only scalar instructions.
Vector processors gain a further speed advantage over scalar processors by their use of special hardware techniques designed for the fast processing of streams of data. These techniques include data pipelining, chaining, and other forms of hardware parallelism in memory and in arithmetic and logical functional units. Pipelined functional units allow the vector processor to overlap the execution of successive computations with previous computations.
VAX Support for Vector Processing (VAX Only)
The VAX vector architecture includes sixteen 64-bit vector
registers (V0 through V15), each containing 64 elements; vector
control registers, including the vector count register (VCR), vector
length register (VLR), and vector mask register
(VMR); vector functional units; and a set of vector instructions.
VAX vector instructions transfer data between the vector registers
and memory, perform integer and floating-point arithmetic, and execute
processor control functions. A more detailed description of the
VAX vector architecture, vector registers, and vector instructions
appears in the VAX MACRO and Instruction Set Reference Manual.
Those VAX systems that comply with the VAX vector architecture are known as vector-capable systems.
A VAX vector processing system configuration includes one or more integrated scalar-vector processor pairs, or vector-present processors. Such a configuration can be symmetric, including a vector coprocessor for each scalar, or asymmetric, incorporating additional scalar-only processors. Depending upon the model of the VAX vector processing system, the scalar and vector CPUs of vector-present processors can be either a single, integral physical module or separate, physically independent modules. In either case the scalar and vector CPUs are logically integrated, sharing the same memory and transferring data over a dedicated, high-speed internal path.
Like VAX scalar processing systems, a VAX vector processing system can participate as a member of a VAXcluster or a node in a network, or be run as a standalone system.
VAX Vector Instruction Emulation Facility
(VAX Only)
The VAX Vector Instruction
Emulation Facility (VVIEF) is a standard feature of the OpenVMS
operating system that allows vectorized applications to be written
and debugged in a VAX system in which vector processors are not
available. VVIEF emulates the VAX vector processing environment,
including the nonprivileged VAX vector instructions and the vector
system services. Use of VVIEF is restricted to user mode code.
VVIEF is strictly a program development tool, and not a run-time replacement for vector hardware. Vectorizing applications to run under VVIEF offers no performance benefit; vectorized applications running under VVIEF execute more slowly than their scalar counterparts.
The operating system supplies the VVIEF bootstrap code as an executive loadable image. Note that, in the presence of OpenVMS vector support code, VVIEF remains inactive. Although it is possible to prevent the loading of vector support code in a vector-present system (see Loading the Vector Processing Support Code (VAX Only)) and activate VVIEF, there are few benefits.
See Loading the VAX Vector Instruction Emulation Facility (VVIEF) (VAX Only) for additional information about loading and unloading VVIEF.
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