From pat+@transarc.com Sun Oct 8 09:37:34 1995 If-Type-Unsupported: send From: ubie@rzstud1.rz.uni-karlsruhe.de (Leonhard Schneider) X-Newsgroups: vmsnet.pdp-11 Subject: NanoNote: QBUS CPUs, features overview (was: LSI-11 chip overview) Followup-To: vmsnet.pdp-11 Date: 7 Oct 1995 09:30:55 +0100 Organization: University of Karlsruhe, Germany Lines: 475 Message-Id: <455drv$ht@rzstud1.rz.uni-karlsruhe.de> Nntp-Posting-Host: rzstud1.rz.uni-karlsruhe.de Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Nntp-Posting-User: ubie To: Info-PDP11@transarc.com X-Gateway-Source-Info: USENET This is a summary of the answers I received from Alan R. Sieving (*ARS*) Chuck O'Toole (*COT*) John Wilson (*JW*) Megan B. Gentry (*MBG*) Pete N. Turnbull (*PNT*) Roger Ivie (*RI*) Ron Natalie (*RN*) and the info I picked from various microcomputer processor handbooks, and in mini-FAQS of Ronald Copley (*RC*) field-guide.txt pdp-11.modules Terry Kennedy (*TK*) Chip.history TOEM MicroNotes micronote.txt resulting in this NanoNote. Table of Contents ================= 1. CPU-typical Features of Chips and Boards (List 1) 2. CPU Chip(set)s 3. Option Chips 4. Option Boards 5. Memory and Peripheral Features of CPU boards(List 2) 6. Additional Comments Please keep in mind that this overview may still be incomplete or even erroneous. The lists are structured in a way that each line shows a possible combination of base chip(set) and option(s), ordered with increasing performance. There are lines which show names of options. IMHO it's best and clearest to order lists to provide 1 line for any existing example CPU-board, because this allows to distinguish between boards - not allowing a peculiar option at all, - sockets/spare locations prepared to upgrade, - installed option. In fact there are 2 lists: - one for CPU-typical features, and - another one for on-board memory/peripheral features. I used these indicators: *** integrated in basic CPU chip(set). --- not installable $$$ optional (socket/spare locations prepared) +++ disabled %%% probably planned, but never available jxxxx joint instruction/data space sxxxx separate instruction/data space 1. CPU-typical Features of Chips and Boards ======================================== =============================================================================== Chipset: Boards: Example: ODT EIS FIS MMU Addr FP11 FPA CIS Notes ------------------------------------------------------------------------------- D11 KD11-* KD11-H* *** $$$ $$$ --- j64kB --- --- --- KD11-F* *** $$$ $$$ --- j64kB --- --- --- KD11-J *** $$$ $$$ --- j64kB --- --- --- KD11-F? *** ??? ??? --- j64kB --- --- ?dibol? /*2 KD11-Q *** ??? ??? --- j64kB --- --- ?dibol? /*2 * *** KEV11 --- j64kB --- --- --- * *** KUV11-AA --- j64kB --- --- --- .............................................................................. F-11 KDF11-* KDF11-AC *** *** --- --- j64kB --- --- --- ???????? *** *** --- $$$ j64kB $$$ --- $$$ KDF11-AA?*** *** --- ??? j4MB $$$ --- $$$ /*2 ???????? *** *** --- $$$ j4MB $$$ --- KEF11-BB KDF11-B* *** *** --- $$$ j4MB $$$ --- ??? KDF11-AA *** *** --- KFT11-AA j4MB $$$ --- $$$ ???????? *** *** --- KTF11-AA j4MB $$$ --- KEF11-BB KDF11-AB *** *** --- KFT11-AA j4MB KEF11-AA --- $$$ ???????? *** *** --- KTF11-AA j4MB KEF11-AA --- KEF11-BB * *** *** --- ??? j4MB FPF11-A --- ??? ............................................................................. J-11 KDJ11-* KDJ11-AA *** *** --- *** s4MB *** --- --- KDJ11-B *** *** --- *** s4MB *** --- --- KDJ11-BA *** *** --- *** s4MB *** $$$ ??? KDJ11-BB *** *** --- *** s4MB *** $$$ ??? KDJ11-D* KDJ11-S* KDJ11-AC *** *** --- *** s4MB +++ FPJ11-AA ??? KDJ11-BD *** *** --- *** s4MB +++ FPJ11-AA ??? KDJ11-BF *** *** --- *** s4MB +++ FPJ11-AA ??? KDJ11-E* *** *** --- *** s4MB +++ FPJ11-AA ??? ???????? *** *** --- *** s4MB +++ FPJ11-AA %%% ============================================================================ T-11 KXT11-* KXT11-A $$$ *** --- --- j64kB --- --- --- KXT11-A* $$$ *** --- --- j64kB --- --- --- KXT11-BA $$$ *** --- --- j64kB --- --- --- KXT11-CA $$$ *** --- --- j64kB --- --- --- * KXT11-A2 *** --- --- j64kB --- --- --- /*1a * KXT11-A5 *** --- --- j64kB --- --- --- /*1b ............................................................................. J-11 KXJ11-* KXJ11-CA *** *** --- *** s4MB *** --- --- KXJ11-?? *** *** --- *** s4MB *** ??? --- ============================================================================= Notes: /*1a according to (*PNT*) /*1b according to "pdp-11.modules" /*2 according to "field-guides.txt" 2. CPU Chip(set)s ============== D11 "LSI-11", rsp. "LSI-11/2" four 40pin DIL ICs: - Control Chip ?????, part number: 23-002C4 - Data Chip ?????, part number: 21-11549-01 or 21-15549-00 - Microm 0 ?????, part number: 23-002B5 - Microm 1 ?????, part number: 23-001B5 basic instruction set incl. SOB, MARK, RTT, SXT Joint Instruction/Data space F-11 "Fonz" ?DCF11? single 40pin DIL 2chip hybrid: - Data Unit (ALU) DC302, 302H, part number: 21-15541AB - Control Unit (microcode) DC303, 302A, part number: 23-001C7 incl. SOB, MARK, RTT, SXT, MFPT, incl. MFPD, MFPI, MTPD, MTPI, Joint Instruction/Data space J-11 "Jaw" single 60pin DIL 2chip hybrid (?DCJ11?) - ??? DC334, part number: 21-17679-10 - ??? DC335, part number: 21-17677-01 incl. SOB, MARK, RTT, SXT, MFPT, SPL, CSM incl. MFPD, MFPI, MTPD, MTPI, includes FPU (Floating Point Unit): 17xxxx: Separate Instruction/Data spaces T-11 "???" single 40pin DIL IC (?DCT11?) incl. SOB, RTT, SXT excl. MARK, ASH, ASHC, DIV, MUL, XOR, HALT (therefore) no microcoded ODT Joint Instruction/Data space 3. Option Chips ============ ODT (Octal Debugging Technique): This isn't an instruction set option, but a little monitor built in to let you examine and modify memory and registers; usually while the machine is halted. It's integral microcode of D11, F11, and J11 CPU's , and optional to T11 (no microcode). KXT11-A2 (ODT program ROM option), a pair of 2Kx8 PROMs (not microcode) in optional diagnostic ROMs for some Falcon boards. KXT11-A5 (ODT program ROM option), a pair of 8Kx8 PROMs (not microcode) in optional diagnostic ROMs for some Falcon boards. KEV11 (??? microcode ROM option) 40pin DIL IC microcoded ("microm") option for D11 DC???, part number: 23-003B5 (LSI-11, LSI-11/2, PDP-11/03) to cover: - EIS (Extended Instruction Set: Fixed Point Arithmetic): 070xxx..073xxx: MUL, DIV, ASH, ASHC Integer multiply and divide, and multi-bit shift operations; standard on most PDP-11s, but a microcode ROM option for D11: - FIS (Extended Instruction Set: Floating Point Arithmetic): 07500x..07503x: FADD, FSUB, FMUL, FDIV Instructions for single-precision floating point. This was a substandard set of floating-point codes. Few machines had it, most either had nothing or the full FP-11 set, which used different opcodes. ??? (DIBOL microcode ROM option): DC??? ??pin ???: KTF11-AA (Memory Management Unit) 40pin custom array option for F-11 - Logic DC304, 304E, part number: 21-15542-01 contains memory management registers and logic, and also accumulator registers for the KEF11-AA (in the very first release these registers were inaccessible). There is no MMU option for D11 or T11 processors; the J11 has an integral MMU. This is a functional unit in the address path for 22bit/4MB addressing; There is only one type of MMU (with the caveat that the very first release MMUs had a fault in the FP registers, but that is an entirely separate issue). I/D (separate Instruction/Data space) is a feature of the MMU implementation. KDF11-B3 (???): DC??? ??pin ? KEF11-AA (Floating Point microcode ROM option) DC??? 40pin DIL 2chip hybrid for F-11 - 303D part number: 23-002C7 - ???? part number: 23-203C7 requires KTF11 (MMU holding accumulator registers). KEF11-BB (Commercial Instruction Set ROM Option) Six chips surface-mounted on a double-width 40-pin carrier for F-11 to provide: CIS (Commercial Instruction Set: Character and Decimal String Instructions): 076xxx: primarily as an aid to COBOL programming. The CIS is just microcode and doesn't need the MMU. FPJ11-AA (Floating Point Accelerator): FPJ11 ??pin option for J-11 Early KDJ11 boards do NOT work with this option. 17xxxx: Single- or double-precision floating point operations. 4. Option Boards ============= KUV11-AA (M8018) WCS (Writable Control Store) option for the 11/03 machine. This is a quad-height board which has a cable connecting to the CPU board (location of KEV11 option socket), and allows you to write and debug your own microcode (up to 1024 words). FPF11-A (M8188) This is a co-processor on a quad-height board for KDF11 processors only; it has a cable connection to the KEF11-AA socket on the KDF11 board (requires "main" CPU with F-11 chipset). All 46 floating point arithmetic operations; faster than KEF11-A. The documentation says it does not need the MMU (*PNT*). 5. Memory and Peripheral Features of CPU boards ============================================ ============================================================================= board: option: SZ ROM RAM CACHE LTC SER PAR ----------------------------------------------------------------------------- KD11-HA M7270 2 --- ---- ----- --- --- --- KD11-J M7264-YA 4 --- ---- ----- --- --- --- KD11-Q M7264-YB 4 --- ---- ----- --- --- --- KD11-F M7264 4 --- 8kB ----- --- --- --- ............................................................................. board: option: SZ ROM RAM CACHE LTC SER PAR ----------------------------------------------------------------------------- KDF11-AA M8186-YA 2 --- --- ----- --- --- --- KDF11-AB M8186-YB 2 --- --- ----- --- --- --- KDF11-AC M8186-YC 2 --- --- ----- --- --- --- KDF11-BA M8189 4 KDF11-B3 --- ----- ??? --- --- KDF11-BF M8189 4 KDF11-B3 --- ----- ??? --- --- ............................................................................. board: option: SZ ROM RAM CACHE LTC SER PAR ----------------------------------------------------------------------------- KDJ11-A* 2 ?? ?? ---- ? ? --- KDJ11-A* 2 ?? ?? 8kB ? ? --- KDJ11-BA 4 2x 8kB * 2xSLU --- KDJ11-BB 4 2x 8kB * 2xSLU --- KDJ11-BD M8190 4 2x 8kB * 2xSLU --- KDJ11-DA M7554-* 4? --- 512kB 8kB * 2xSLU --- KDJ11-DB M7554-* 4? --- 1.5MB 8kB * 2xSLU --- KDJ11-SA 4? --- 512kB 8kB ? 2xSLU --- KDJ11-SB 4? ??? 512kB 8kB ? 2xSLU --- KDJ11-EA 4? ??? 2.0MB 8kB ? 8xSLU --- KDJ11-EB 4? ??? 4.0MB 8kB ? 8xSLU --- .............................................................................. board: option: SZ ROM RAM CACHE LTC SER PAR DMA TIMER ------------------------------------------------------------------------------- KXT11-AA M8063-AA 2 ???? 4kB ??? *** 2 SLU 24Lines --- /*B KXT11-BA M8063-BA 2 ???? 16kB ??? *** 2 SLU 24Lines --- /*B KXT11-AB M7676 2 $$$$ 16kB ??? *** 2 SLU 24Lines --- /*B 2 ---- 32kB ??? *** 2 SLU 24Lines --- /*B 2 ---- 48kB ??? *** 2 SLU 24Lines --- /*B 2 16kB 16kB ??? *** 2 SLU 24Lines --- /*B 2 32kB 16kB ??? *** 2 SLU 24Lines --- /*B KXT11-CA M8377 4 $$$$ 32kB ??? *** 1+2SLU 20Lines 2Ch 3 /*C 4 ---- 64kB ??? *** 1+2SLU 20Lines 2Ch 3 /*C 4 32kB 32kB ??? *** 1+2SLU 20Lines 2Ch 3 /*C ............................................................................. board: option: SZ RAM ROM CACHE LTC SER PAR ----------------------------------------------------------------------------- KXJ11-?? M???? 4 /*B 2 async serial ports /*C 1 async console port + 2 sync/async serial ports 6. Additional Comments =================== Note about Floating Point opcodes --------------------------------- (*PNT*): I want to point out that FIS and regular FP opcodes are different. The last time I had to think about it was for the last sysgen I did on RSX (at least three years ago), and I've certainly never felt inclined to do FP arithmetic in MACRO-11! (For those who're interested, FIS instructions are stack-based while FP11 ops are much more extensive and can be stack-based or register-based). FIS of course only exists on the D11 - as the KEV11 option - while the F11 supports 'proper' floating point as a microcode option (KDF11-AA) or accelerator (FPF11), the J11 supports it in native microcode, or in faster form with the FPJ11 coprocessor, and the T11 has no FP operations at all. Incidentally, my KDJ11 reference card shows the FIS instructions, though they're not in the Technical Manual. So I tried them on my KDJ11-A's - and wasn't surprised to find they're trapped as illegal instructions. Since the microcode mostly exists anyway (for certain uses of the regular FP ops), I wonder if someone at Digital once thought they might be included for some sort of compatibility reason? Note about DIBOL microcode option --------------------------------- (*PNT*) Well, you got my curiousity aroused, so I did some checking. It seems that Dibol is a DEC-specific version of Cobol, and we know that CIS was to aid Cobol compilers in producing fast code, so it looks like the "Dibol microcode" is actually the CIS option. I looked up a Systems and Options catalogue for early 1980's, and it mentions Dibol and CIS (not on the same page) but nothing else. Note about KDF11-* ------------------ (*PNT*): Some CPU boards with MMU options installed allowed just 18bit/256kB addressing. This only applies to KDF11-Ax, and it depends entirely on the board's CS Revision Level: the first release CS Rev.A only had 18-bit addressing, all others (standard is CS Rev.C, there was no B release) including all KDF11-Bx are 22-bit. The -AC suffix means the MMU is not fitted, -AA means it is. The -AA and -AC have *nothing* to do with CS Rev.A and CS Rev.C. Also, a KDF11-Bx is the quad board, PDP 11/23+, or microPDP-11/23, depending on the ROMs fitted and the box it's in. Any of these can have CIS, FPP, or FPA as upgrades. All were sold with MMUs (though they will still work without. However, I believe some of the ROMs assume the MMU is fitted). Note about KDJ11-* ------------------ (*PNT*): All the KDJ11-Ax are dual CPU boards, the KDJ11-Bx are quads with integrated bootstrap,LTC, SLUs, etc. Early -Ax come in three forms: 1) has FPA socket, but it doesn't work (see notes from sunsite) 2) has no FPA socket 3) has working FPA socket KDJ11-Ax were sold as OEM products, or as upgrades to 11/23 systems. As far as I know, all KDJ11-Bx have working FPA sockets. However, some KDJ11-Bx have a 15MHz clock, and some have 18MHz. KDJ11-Bx were sold primarily as microPDP-11/73 (KDJ11-BB, -BC) or microPDP-11/83 (-BF) and the only differences are the ROMs. However, all -BF boards I've seen are 18MHz, and most -BB/-BC are 15MHz. And the difference between an 11/73 and an 11/83 is that the 11/83 used PMI memory (but all 73's can be upgraded by replacing the memory and moving the CPU). I can't remember which is which, but one of the boards (-D? -S?) is the microPDP-11/53, which is like a slow microPDP-11/73 but with memory on-board (either 0.5MB or 1.5MB depending on configuration/price) and there's another board which is the microPDP-11/93. The /83 and /93 boards are also used in /84 and /94 Unibus machines. Finally, all KDJ11's have 8KB fast cache memory. Note about KXT11-* ------------------ (*PNT*): The T11 was intended as a slave processor or as support processor, and appears in - RQDXn controllers, - the Single Board Microcomputers (SBC's: Falcon 11/21, and Falcon-Plus), and - DENUA Ethernet controllers. All the T11-based devices have a 64KB address range. There's - no MARK instruction, - no HALT (trying to execute it causes a trap), - no MMU, - no EIS, etc. The registers are not memory-mapped but the addresses normally associated with the registers *are* memory-mapped, so accessing the addresses doesn't cause an abort the way it would on an F11 or J11. There are several other minor differences from 'mainstream' CPUs. The Falcon, aka 11/21, aka SBC, M8063-AA has 4KB (?16kB?) static RAM and 4 28-pin sockets which can hold RAM or ROM. Normally one pair has the monitor/diagnostic ROMs. All M8063's have - 2 SLUs, - 24 parallel I/O lines (two 8-bit I/O ports and an 8-bit control port, which does various on-board things), - a line clock (settable to 50/60/800Hz) using IRQ level 6 (not 4) and driving the BEVENT line. Someone else can probably tell which, but I know that one of the other boards you list is the slave processor for use under RT-11 using the KX: device driver. It seems that the A5 (8K x 8) option is indeed a bigger ROM set for the -AB boards, but it seems (from the catalogue) to have much the same functionality as the A2 (2K x 8) for -AA boards: The -AA is 4K RAM plus 4 x 28-pin sockets for RAM or ROM (normally one pair has the -A2 ROMs); max 8K (?16kB?) RAM, 8+8 (+8 control bits) I/O, 2 SLUs, 16-bit addressing, no MMU, no EIS/FIS, LTC running at 50/60/800 Hz, LTC interrupt at level 6 (instead of 4), registers are not memory mapped but neither are the standard register addresses trapped (as they are on most other Q-bus processors). The -AB has 8K RAM, and it looks like the sockets are rewired to be able to take larger capacity devices; otherwise, it's the same board. The -AC is the one intended for use as a co-processor, with a KDF11 or KDJ11 as host, running RT11 or RSX11. However, the -CA can be used on it's own. The -CA has 3 SLUs, 20-bit I/O (says the catalogue), three interval timers, 32K RAM, 2 spare sockets for ROM, 2 DMA controllers, some LEDs. (*COT*): The KXT-11 board, Q-bus based, was a programmable slave board that could be used to offload some process control or other functions from the main processor. It had a parallel port on-board and a "downline load" protocol firmware. Drivers provided for message passing between the main processor (running RSX-11M) and the KXT-11 application (MicroPower/Pascal). (*RI*): RQDX3 is also T-11 based. This was fun for the hardware guys because the T-11 never does a write cycle without a previous read (all T-11 writes look like read-modify-write cycles; rumor is they saved some microcode that way) and th 9224 hard disk controller moves its internal register pointer after each access. They wound up decoding the 9224 in two different address spaces depending on whether they wanted to read or write it. -- Leonhard Schneider *** eMail ubie@rz.uni-karlsruhe.de