Article 4488 of vmsnet.alpha:
Stephen Hoff Hoffman (hoffman@xdelta.enet.dec.com) wrote:

: In article <32117674.2781@adv.magwien.gv.at>, Ferry Bolhar-Nordenkampf <bol@adv.magwien.gv.at> writes:
: :-- 
: :i know that the Alpha has 64-bit registers and that every instruction
: :requires 32 bits.

:   If you are using the Macro32 *Compiler*, you program as if you were
:   on a VAX, not an Alpha.

:   If you are programming with the Alpha *assembler* (Macro64), *then*
:   you need to deal with the Alpha instruction format.

: :Now my question: how to load a 64-bit literal into a register when
: :only 32 bits for the instruction are available?

:   LDL or LDQ (load-long, load-quad), or LDA or LDAH (address loads).

This is fine for up to 32 bits, but the original question was for 64 bits.
It can be extended to 64 bits, 16 bits at a time.

An alternative is to use PC based addressing.  But any attempt to actually
place a greater than 16 bit literal in the instruction stream is going to
cause a cache miss, and therefor degrade performance (I had a macro to do this,
but I intentionally deleted all my copies).  Much better, put the datum in the
linkage section.

I have a macro to do this:

;++
; Macro to load a quad or long
; Assumes a base register for the linkage section has been defined
;--
	.macro	ldi	reg,value,size=quad,?l1

	.save_psect	; save code psect we're in

	; a data psect for this code, must be aligned

	$linkage_section
	.align	size
l1:	.'size	value

	.restore_psect	; back to the code psect

	.if	IDN size quad
	 ldq	reg,l1

	.iff
	 .if	IDN size long
	  ldl	reg,l1

	 .iff                                   
	  .error	"size is not quad or long"

	 .endc
	.endc

        .endm


------------------------------------------------------------------------------
Bob Koehler                     | CSC/SSD/MITG
rkoehler@csc.com                |


