From: leslie@clio.rice.edu
Sent: Friday, September 22, 2000 8:33 AM
To: Info-VAX@Mvb.Saic.Com
Subject: SRAM Corruption Thread

There's a thread on SRAM corruption going on in these newsgroups:

   sci.physics, comp.arch.embedded, comp.realtime

where the attached article came from.

--Jerry Leslie     (my opinions are strictly my own)
==============================================================================
From: Ian BARNETT <Ian.Barnett@cern.ch>
Newsgroups: sci.physics,comp.arch.embedded,comp.realtime
Subject: Re: SRAM Corruption when traveling abroad
Date: Fri, 22 Sep 2000 08:37:45 +0200
Organization: CERN
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Hi list

	We are having the same problem here at CERN and are studying neutron
radiation effects on SRAMs. The main problem is single event latchup -

http://www.aero.org/seet/primer/single_event_latchup.html

We are now designing EDAC (error detection & correction ) circuits in
FPGAs to overcome this problem.

Ian Barnett
CERN
European Orginisation for Nuclear Research

Bruce wrote:
> 
> In comp.realtime
> "William R. Frensley" <frensley@utdallas.edu> wrote:
> 
> >One question is what is the SRAM implementation?  A full 6-transistor CMOS
> >cell should be very robust against any random charge-generating events,
> >since each node of the circuit always has a low-impedance path to power or
> >ground.
> 
> It is 6 transistor CMOS and the effect is a very real problem, especially
> for electronics in space.  Here are some links if you're interested:
> 
> http://nepp.nasa.gov/imd/eee_links/vol_02/no_01/eee2-1r.htm
> Description of the CRUX (Cosmic Ray Upset eXperiment)
> 
> http://chemistry.about.com/science/chemistry/library/weekly/aa052200a.htm
> A bunch of links to articles
> 
> http://www.mitsubishichips.com/press/releases/fsram_99.htm
> A Misubishi press release announcing their new cosmic ray resistant SRAM
> for laptops.
> 
> Bruce